A number of parameters may be used to describe the characteristics of an electrical signal. These parameters include voltage amplitude, frequency, period, duty cycle, on-time and off-time. Duty cycle is particularly relevant to signals having a digital or rectangular waveform. Digital or rectangular waveforms typically alternate between a low voltage level and a high voltage level, with the transition between voltage levels occurring substantially instantaneously. The term "period" refers to the duration of a single cycle. For each cycle, a digital or rectangular waveform remains at the low voltage level for a portion of the period, and at the high voltage level for the remainder of the period. "On time" refers to the amount of time a digital or rectangular waveform remains at the high voltage level, while "off-time" refers to the amount of time a digital or rectangular waveform remains at the low voltage level. "Duty cycle" refers to the ratio of on time to period, and is often specified as a percentage. A digital or rectangular waveform signal may have a duty cycle ranging from zero to 100 percent. In some cases, the duty cycle of a signal may be unpredictable. To make the characteristics of this type of signal more predictable, it is often desirable to adjust the duty cycle of the unpredictable signal to a known value, such as 50 percent. A 50 percent duty cycle provides equal on time and off time for each period.
In the prior art, methods for controlling the duty cycle of an input signal have been reported. For example, a known way to adjust an input signal to a 50 percent duty cycle output signal is through the use of a phase locked loop (PLL). As shown in FIG. 1, the incoming clock frequency (f) is first doubled to 2f by the PLL voltage controlled oscillator (VCO), and is then divided with a 2:1 divider, such as a D flip-flop, to provide a 50% duty cycle output signal, as well as a 50% duty cycle feedback signal to the PLL phase detector. There are two disadvantages to this type of duty cycle control, however, as described below:
(1) power consumption is increased due to the PLL circuit operating at twice the frequency; and
(2) a complex analog design of the VCO is required, which is expensive, both in terms of implementation costs, and integrated circuit "real estate".
Another prior art method for controlling the duty cycle of a signal is described in U.S. Pat. No. 4,479,216, issued to Krambeck, et al. Krambeck describes a circuit, as shown in FIG. 2, in which the average voltage (V+) of a clock out pulse (at node t7) is compared to a reference voltage (VDD/2) in an operational amplifier. The OPAMP output (Vfb) is fed back to transistors MP2 and MN1 to alter the timing of the clock pulses inputted to pullup transistor MP1 and pulldown transistor MN2, thereby controlling the rise time and fall time of the output pulse at node t2. Since the operating frequency of the entire circuit is the same as that of the input clock signal, this circuit consumes less power than the frequency doubling PLL prior art described above. However, this circuit does tend to have a loop stability problem under certain conditions. For example, the duty cycle of an unpredictable input clock signal may vary from 20 percent to 80 percent. Although the duty cycle may change, its frequency remains the same. Therefore, for a pre-determined operating frequency, the time constant of the RC low pass filter (integrating circuit) remains the same. As a result, when an input clock signal has a duty cycle greater than 50 percent, the disclosed circuit tends to have an unstable loop function. The instability occurs because the NMOS transistor of the input stage (MN2) may be turned on for a longer time period than the feedback signal Vfb is able to control via transistor MN1.
Accordingly, it is an object of the present invention to provide an improved method and circuit for adjusting the duty cycle of a clock signal, which overcomes the main disadvantages of the prior art; namely: (1) to consume less power than the frequency doubling PLL approach; and (2) to provide a stable loop function regardless of the duty cycle of the input signal.